1. Field of the Invention
The present invention relates to a backlight driving apparatus, and more particularly to a backlight driving apparatus of a liquid crystal display that is adaptive for receiving a power voltage for burst dimming via one power terminal to simultaneously adjust a burst dimming and an analog dimming, and a driving method thereof.
2. Description of the Related Art
Generally, a liquid crystal display controls light transmittance of liquid crystal cells in accordance with video signals to thereby display a picture. An active matrix type of liquid crystal display having a switching device provided for each liquid crystal cell is advantageous for an implementation of moving picture because it permits an active control of the switching device. The switching device used for the active matrix liquid crystal display mainly employs a thin film transistor (hereinafter, referred to as “TFT”) as shown in FIG. 1.
Referring to FIG. 1, the liquid crystal display of the active matrix type converts a digital input data into an analog data voltage on the basis of a gamma reference voltage to supply it to a data line DL and, at the same time supply a scanning pulse to a gate line GL, thereby charging a liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL, a source electrode is connected to the data line DL, and a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and one end electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
When the TFT is turned-on, the storage capacitor Cst charges a data voltage applied from the data line DL to constantly maintain a voltage of the liquid crystal cell Clc.
If the gate pulse is applied to the gate line GL, the TFT is turned-on to define a channel between the source electrode and the drain electrode, thereby supplying a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. In this case, liquid crystal molecules of the liquid crystal cell Clc are arranged by an electric field between the pixel electrode and the common electrode to modulate an incident light.
A configuration of the related art liquid crystal display including pixels which have such a structure is the same as shown in FIG. 2.
FIG. 2 is a block diagram showing a configuration of the related art liquid crystal display.
Referring to FIG. 2, a liquid crystal display 100 includes a liquid crystal display panel 110, a data driver 120, a gate driver 130, a gamma reference voltage generator 140, a backlight assembly 150, a common voltage generator 160, a gate driving voltage generator 170, a timing controller 180, and an inverter 190. Herein, the data driver 120 supplies a data to the data lines DL1 to DLm of the liquid crystal display panel 110. The gate driver 130 supplies a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110. The gamma reference voltage generator 140 generates a gamma reference voltage to supply it to the data driver 120. The backlight assembly 150 irradiates a light onto the liquid crystal display panel 110. The common voltage generator 160 generates a common voltage Vcom to supply it to a common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110. The gate driving voltage generator 170 generates a gate high voltage VGH and a gate low voltage VGL to supply them to the gate driver 130. The timing controller 180 controls the data driver 120 and the gate driver 130. The inverter 190 applies an AC voltage and a current to the backlight assembly 150.
The liquid crystal display panel 110 has a liquid crystal dropped between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn perpendicularly cross each other. Each intersection between the data lines DL1 to DLm and the gate lines GL1 to GLn is provided with the TFT. The TFT supplies a data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. The gate electrode of the TFT is connected to the gate lines GL1 to GLn while the source electrode thereof is connected to the data line DL1 to DLm. Further, the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and to the storage capacitor Cst.
The TFT is turned-on in response to the scanning pulse applied, via the gate lines GL1 to GLn, to the gate terminal thereof. Upon turning-on of the TFT, a video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.
The data driver 120 supplies a data to the data lines DL1 to DLm in response to a data driving control signal DDC which is supplied from the timing controller 180. Further, the data driver 120 converts digital video data RGB which are supplied from the timing controller 180 into an analog data voltage on the basis of a gamma reference voltage from the gamma reference voltage generator 140 to supply it the data lines DL1 to DLm. Herein, the analog data voltage is realized as a gray scale at the liquid crystal cell Clc of the liquid crystal display panel 110.
The gate driver 130 sequentially generates a scanning pulse in response to a gate driving control signal GDC and a gate shift clock GSC which are supplied from the timing controller 180 to supply it to the gate lines GL1 to GLn. In this case, the gate driver 130 determines a high level voltage and a low level voltage of the scanning pulse in accordance with the gate high voltage VGH and the gate low voltage VGL which are supplied from the gate driving voltage generator 170.
The gamma reference voltage generator 140 receives a high-level power voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and output them to the data driver 120.
The backlight assembly 150 is provided at the rear side of the liquid crystal display panel 110, and is radiated by an AC voltage and a current which are supplied from the inverter 190 to irradiate a light onto each pixel of the liquid crystal display panel 110.
The common voltage generator 160 receives a high-level power voltage VDD to generate a common voltage Vcom, and supplies it to the common electrode of the liquid crystal cell Clc provided at each pixel of the liquid crystal display panel 110.
The gate driving voltage generator 170 is supplied with a high-level power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL, and supplies them to the gate driver 130. Herein, the gate driving voltage generator 170 generates a gate high voltage VGH more than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110 and a gate low voltage VGL less then the threshold voltage of the TFT. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used for determining a high level voltage and a low level voltage of the scanning pulse generated by the gate driver 130, respectively.
The timing controller 180 supplies digital video data RGB which are supplied from a system such as a TV set or a computer monitor, etc to the data driver 120. Furthermore, the timing controller 180 generates a data driving control signal DCC and a gate driving control signal GDC using horizontal/vertical synchronization signals H and V in response to a clock signal CLK to supply them to the data driver 120 and the gate driver 130, respectively. Herein, the data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL and a source output enable signal SOE, etc. The gate driving control signal GDC includes a gate start pulse GSP and a gate output enable signal GOE, etc.
The inverter 190 receives a power voltage for burst dimming of 0V to 3.3V from a system to generate a burst dimming signal, and then adjusts a duty ratio of a pulse width modulating signal PWM which is used for generating a driving current of the backlight assembly 150 in accordance with the burst dimming signal. At the same time, the inverter 190 alternatively receives a power voltage for analog dimming of 0V, 1.65V, and 3.3V from a system to adjust amplitude of a pulse width modulating signal PWM.
Such an inverter 190 adjusts a supply period of a driving current of the backlight assembly 150 in proportion to a duty ratio of a pulse width modulating signal PWM and, at the same time adjusts amplitude of a driving current of the backlight assembly 150 in proportion to amplitude of a pulse width modulating signal PWM. Herein, the inverter 190 receives a power voltage for burst dimming via one power terminal and receives a power voltage for analog dimming via the other power terminal.
In this way, a backlight driving apparatus of the related art, that is, since the inverter 190 receives a power voltage for burst dimming and a power voltage for analog dimming via two power terminals, respectively, a system is designed to separately supply a power voltage for burst dimming and a power voltage for analog dimming. The inverter 190 of the related art has a disadvantage in that a configuration of supplying power path and a circuit configuration of the system are complicated.